Bibliographic Metadata

Advanced interface and control architectures for multi-standard RF transceivers / Siegfried Brandstätter
Additional Titles
Advanced interface and control architectures for multi-standard RF transceivers
AuthorBrandstätter, Siegfried
CensorHuemer, Mario ; Springer, Andreas
DescriptionXIV, 162 S. : graph. Darst.
Institutional NoteKlagenfurt, Alpen-Adria-Univ., Diss., 2013
Abweichender Titel laut Übersetzung der Verfasserin/des Verfassers
Bibl. ReferenceOeBB
Document typeDissertation (PhD)
Keywords (DE)RF Transceiver / Echtzeitsteuerung / MPSoC / On-Chip Synchronisation / On-Chip Kommunikation / applikationsspezifisches Processordesign / applikationsspezifisches NoC-Design
Keywords (EN)RF transceiver / real-time controlling / MPSoC / on-chip synchronization / on-chip communication / application-specific processor design / application-specific NoC design
Keywords (GND)Mobile Telekommunikation / Radiofrequenzbereich / Transceiver / Schnittstelle / Regelungssystem
URNurn:nbn:at:at-ubk:1-11165 Persistent Identifier (URN)
 The work is publicly available
Advanced interface and control architectures for multi-standard RF transceivers [8.17 mb]
Abstract (German)

The ever growing amount of data transmitted in mobile communication networks leads to demand for new mobile communication standards which are not only able to provide higher data rates but also to increase the utilization of the available frequency spectrum. These enhancements continuously increase the complexity of mobile communication systems and especially challenge the design of components for mobile devices which are notably restricted in the power consumption, the silicon area, and the costs.

Over the years, the radio frequency (RF) transceiver has become a complex mixed signal system-on-chip (SoC) integrating analog signal processing, digital signal processing, as well as control processing.

Due to various influences, the control processing experiences a tremendous increase in complexity which cannot be handled by traditional approaches. Therefore, this thesis focuses on the partitioning of RF transceiver systems and the implementation of hard real-time controlling in multiprocessor systems-on-chip (MPSoCs) to introduce an advanced digital interface and control architecture which is able to fulfill the requirements of future RF transceiver integrations.

In general, the novel architectural approach is based on a distributed controlling concept which partitions the RF transceiver into stand-alone units capable of controlling themselves. Considering the strict real-time requirements, the concept makes use of a common time base which is needed to synchronize the distributed units. Furthermore, an application-specific network-on-chip (NoC) and an application-specific reduced instruction set computer (RISC) core are developed to enable the on-chip communication and the control processing.

The proposed framework demonstrates a high degree of scalability, flexibility, and reusability for the integration of future RF transceivers. Consequently, the time to market for products can be reduced and fast adaptations to the requirements of the market are feasible. These are important parameters to be competitive. Moreover, the application-specific designs, which are developed for the novel architectural approach, provide an excellent overall performance.

Compared to common architectures, the concepts achieve better or at least equivalent performance results while the silicon area can be reduced. This characteristic has positive effects on the costs as well as on the power consumption of the RF transceiver.

Even though the advanced interface and control architecture has to prove itself in the productive environment, the advantages of concept are already noticed and particular considerations are incorporated in upcoming RF transceiver integrations.

Abstract (English)

Keine Zusammenfassung vorhanden

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